This invention relates to a dynamic semiconductor memory device and more particularly to a precharge circuit system for bit lines for suppressing current consumption in the stand-by state even if the defect of short circuit occurs between a bit line and a word line.
As the processing technology of semiconductor substrates is more developed, the size of elements used in the semiconductor memory device gradually becomes smaller. Accordingly, the processing pitch of wirings, for example, in the semiconductor memory device is made smaller and the rate of generation of defects of short circuits between wirings due to a fluctuation in the processing caused in the manufacturing process or dusts in a clean room in which the process is effected becomes higher.
In the internal portion of the dynamic semiconductor memory device, generally, word lines and bit lines constituting the matrix of memory cells are arranged with the minimum processing pitch in the chip, whereby the defects of short circuit described above occur most frequently at the portion of the matrix of memory cells than other part of the chip. Particularly, if the defect of short circuit occurs between the bit line and the word line, the current consumption of the chip increases in the stand-by state.
That is, since the word line is fixed at 0V (Vss) in the stand-by state and the bit line is fixed at Vcc/2, the load of a Vcc/2 power supply which is a precharge potential generating circuit for bit lines becomes larger and the current consumption increases if an output of the Vcc/2 power supply is short-circuited to the Vss potential node.
The above state is explained with reference to the accompanying drawings.
FIG. 1 shows an example of the arrangement of a memory cell array and a sense amplifier section. An N-type sense amplifier formed of an N-type MOS transistor, a P-type sense amplifier formed of a P-type MOS transistor, a bit line precharger and a data transfer gate are connected between a bit line BLS and a complementary bit line /BLS of the sense amplifier section. The above circuits are commonly used by cell arrays A and B arranged on both sides of the sense amplifier and the bit lines in the sense amplifier section are connected to or disconnected from the bit lines in the cell array sections according to two control signals .o slashed.A, .o slashed.B. More specifically, the bit line BLA and the complementary bit line /BLA thereof contained in the cell array A are respectively connected to the bit line BLS and the complementary bit line /BLS of the sense amplifier section by activating the control signal .o slashed.A, and the bit line BLB and the complementary bit line /BLB thereof contained in the cell array B are respectively connected to the bit line BLS and the complementary bit line /BLS thereof by activating .o slashed.B.
In the internal portion of the cell array, a plurality of word lines are arranged to cross a plurality of bit lines and memory cells are arranged at the intersections between the bit lines and the word lines.
FIG. 2 is a timing chart for illustrating the operation of the circuit of FIG. 1.
First, in the stand-by state, an EQ signal is activated (Vpp level), both of .o slashed.A and .o slashed.B are activated, and the potentials of all of the bit lines are precharged to Vcc/2 by the bit line precharger. SAN and SAP are also precharged to Vcc/2 like the bit lines and the sense amplifier is kept at the non-active state.
Further, the potential of a column selection signal line CSL is fixed at Vss, that is, 0V, and the bit lines BLS, /BLS and the data lines D, /D are electrically isolated.
Further, the potential of the word line is fixed at Vss, that is, 0V.
When access to the memory cell is started, the EQ signal is disabled, and one of .o slashed.A and .o slashed.B is non-activated. That is, one of the cell arrays corresponding to one of .o slashed.A and .o slashed.B which is kept activated is connected to the sense amplifier. In this example, since .o slashed.B is non-activated and .o slashed.A is kept activated, BLA and /BLA are respectively connected to BLS and /BLS, when BLB and /BLB is disconnected from BLS and /BLS.
Next, the word line is activated to transfer data of the memory cell to the bit line and the potential of the bit line is slightly changed from the precharge potential of Vcc/2.
The variation amount (.increment.V) is expressed by the following equation based on the capacitance Cs of the memory cell, the capacitance CB of the bit line and Vcc. EQU .increment.V=(1/2)Vcc.times.(Cs/CB)
In this case, the bit line capacitance CB can be expressed by the following equation by use of the capacitance CBA of the bit line BLA of the cell array section, the capacitance CBS of the bit line BLS of the sense amplifier section and the cell capacitance Cs. EQU CB=CBA+CBS+Cs
Next, the potential of SAN is changed to Vss, the potential of SAP is changed to Vcc, data on the bit line is amplified and the potentials of the paired bit lines are driven to Vcc and Vss, respectively.
Further, if CSL is selectively activated from Vss to Vcc, bit line pair BLS and /BLS are respectively connected to data line pair D and /D, and the data on BLS and /BLS are transferred to D and /D.
In the operation of the DRAM described above, as the precharge potential of the bit line and that of the word line differ from each other, the bit line is precharge to Vcc/2 and the word line is precharged to Vss, a power consumption becomes a serious problem when the defect of short circuit occurs between the bit line and the word line. That is, if the defect of short circuit occurs between the bit line and the word line, a wasteful current flows between the Vcc/2 power supply and the Vss power supply, thereby increasing the current consumption in the whole chip.
The problem is schematically shown in FIG. 3.
The word line is connected to the Vss power supply and the bit line is connected to the Vcc/2 power supply in the stand-by state, but if the short circuit occurs between them, a current flows in a path as indicated by an arrow in FIG. 3. In the manufacturing specification of the DRAM, generally, a current in the stand-by state is set to be smaller than in the operative state and an increase in the power consumption described above raises the possibility that the chip may be treated as a defective product, even if the defective bit line is replaced by a redundant one.
A known method for solving the above problem is disclosed in "Fault-Tolerant Designs for 256 Mb DRAM" by Toshiaki Kirihata et al., IEICE Trans. Electron Vol. E79-C, No. 7, July 1996, pp. 969-977. In this article, a method for suppressing a current when the defect of short circuit occurs between the bit line and the word line by mounting a current limiting element T as shown in FIG. 4 on the precharge circuit for bit lines is disclosed.
That is, a current flowing between a node A and a node B is limited by inserting a diode-connected N-type MOS transistor T between the node A of the bit line precharge circuit and the node B connected to the output of the Vcc/2 power supply. The transistor T is a depletion type transistor which has a threshold voltage lower than the transistors used in the N-type MOS sense amplifier and can permit a current corresponding to the potential difference between the source and the drain to flow even if the voltage between the source and the gate is 0V, although the current amount is extremely small and is suppressed to approximately 15 .mu.A at maximum. By using the depletion type transistor, a path between the nodes A and B is not completely cut off. Therefore, the bit line can be precharged and since the current is suppressed to 15 .mu.A at maximum, a current of 15 .mu.A or more is not consumed for each defective portion even if the defect of short circuit occurs between the bit line and the word line.
However, with the above method, the total amount of power consumption caused by the short circuit increases with the number of defective portions. That is, since the current limiting element only defines the upper limit of the current caused by the defect of short circuit in one place, a current proportional to the number of defective portions may flow if the defects of short circuit occur in many portions. Therefore, if the number of defects of short circuit becomes larger, it is anticipated that the stand-by current cannot satisfy the specification and the chip may be treated as a defective product.
If a current permitted to flow in one current limiting element is set to an extremely small value, the above problem can be solved. That is, if the current is limited to 1/10 times, the power consumption can be kept constant even if the number of defective portions of short circuit is increased by 10 times.
However, in the above known reference, since the bit line is precharged via the current limiting element, time required for precharging the bit line becomes long if the current amount permitted to flow in the current limiting element is limited to an extremely small value, and therefore, the current cannot be limited to a smaller value than necessary. Even if the current amount permitted by the current limiting element is set to the minimum permissible value which satisfies the required precharge time, an increase in the power consumption proportional to the number of defects of short circuit cannot be avoided.